1. Field of the Invention
The invention relates to a semiconductor device and a method of producing the same, and a semiconductor module, and, more particularly, to reduction in size and improvement in heat radiating capacity of a vertical-type surface mount package, as well as a semiconductor module employing a semiconductor package.
2. Description of the Related Art
A description will be given of a prior art, which serves as the background of the invention, with reference to FIGS. 20 through 30. Referring to FIGS. 20 through 30, reference numeral 1 denotes a semiconductor device; reference numeral 4 denotes a semiconductor chip; reference numeral 6 denotes a die pad; reference numeral 7 denotes a sealing resin; and reference numeral 8 denotes an inner lead. Referring to the same figures, reference numeral 10 denotes an outer lead forming a first lead frame, which extends out from the sealed portion of the lead of the first frame; reference numeral 11 denotes an outer lead of a second lead frame, which extends out from the sealed portion of the lead of the second frame; reference numeral 16 denotes a suspension lead for die pad 6, which connects die pad 6 and an outer portion of a lead frame; reference numeral 24 denotes an outer lead on a lead frame; reference numeral 25 denotes a stand lead, which is longer than the usual outer leads and is bent in the same and opposite directions with respect to the usual leads, for setting upright semiconductor 1 in a conventional SVP package (described later); and reference number 26 denotes a lead frame.
Hitherto, there has been provided a vertical mount package called, "Zigzag In-line Package" (ZIP), shown in FIGS. 20 and 21, for packaging a semiconductor device. In a ZIP, a semiconductor device is set perpendicular to a mounting substrate and mounted thereon. This has allowed it to respond, in particular, to demands such as for higher density mounting (higher mounting density per mounting area), for example, in the memory IC field. [Refer to pp. 99 through 107 of Nikkei Electronics (No. 4), published on Sep. 7, 1987.]
The aforementioned ZIP-type semiconductor device (ZIP) is a so-called through hole device (THD) in which an external lead is soldered by inserting it into a through hole. Besides the aforementioned ZIP, dual in-line package (DIP) type semiconductor devices are also available as a type of THD (shown in FIG. 22), which has been employed as a main package for semiconductor devices.
However, since, in THD, a semiconductor device is mounted by using a through hole in the substrate, only one face of the substrate can be used for mounting. For this reason, with increased demands for higher density mounting, the so-called surface mount device (SMD), which allows mounting on both faces of the substrate, is beginning to replace the THD. Mounting on both faces is achieved by placing the external lead on an electrode (land), disposed on the surface of the substrate, and soldering it thereto.
Although available SMD types include, for example, small out-line package (SOP) semiconductor devices, shown in FIG. 23, and small out-line J-lead (SOJ) semiconductor devices, no ZIP-type semiconductor packages (aforementioned vertical-type surface mount package) exist as standard packages. Accordingly, various companies have proposed various ideas, which include those disclosed, for example, in Japanese Patent Laid-Open No. 2-110960, Japanese Patent Laid-Open No. 3-129866, Japanese Patent Laid-Open No. 3-194954, Japanese Patent Laid-Open No. 5-21684, and Japanese Patent Laid-Open No. 5-55273.
The surface vertical package (SVP), shown in FIGS. 24, 25, and 26, is being considered as a standardized package. However, since in an SVP the external leads are formed on one frame, the use of a larger number of leads results in a package length (length of the side where the leads extend out) which is longer than that required with respect to the chip size. Therefore, in some cases it is not possible to take advantage of the high-density mounting of the vertical-type surface mount package. Likewise, in the semiconductor device packages disclosed in Japanese Patent Laid-Open No. 2-110960, Japanese Patent Laid-Open No. 3-129866, and Japanese Patent Laid-Open No. 3-194954, when a large number of outer leads need to be used, it is necessary to extend the length of the side where the external leads extend out from the package. This has prevented such semiconductors from meeting the demand of high-density mounting.
Ideas have been proposed to overcome such a problem, for example, in Japanese Patent Laid-Open No. 60-180154, Japanese Patent Laid-Open No. 63-66959, and Japanese Patent Laid-Open No. 5-21684, in which when a large number of outer leads are required, the length of the side where the outer leads extend out is reduced by one-half by forming the leads into multiple layers.
Among these publications, Japanese Patent Laid-Open No. 60-180154 and Japanese Patent Laid-Open No. 63-66954 disclose semiconductor packages in which two lead frames are bonded together through a dielectric layer. However, since care must be taken in mounting the electrodes at the substrate side and the semiconductor device is a through hole type device, it is difficult to achieve surface mounting.
Even in the semiconductor package disclosed in Japanese Patent Laid-Open No. 5-21684, extreme care must be taken to carry out mounting at the substrate side, thus preventing it from being used widely. In addition, since the tape automated bonding (TAB) technique is used to mount the semiconductor, it is difficult to simultaneously mount other semiconductor parts during the mounting process. In the semiconductor packages disclosed in the aforementioned Japanese Patent Laid-Open No. 60-180154, Japanese Patent Laid-Open No. 63-66959, and Japanese Patent Laid-Open No. 5-21684, two types of outer leads are bonded together through a dielectric layer and bent in the same direction. Therefore, the thickness of the leads where they are bent is virtually doubled, and there is a difference in curvature R between the two types of outer leads in the bending process, so that the leads are displaced with respect to each other. For this reason, it is difficult to process the leads, and in some cases, dielectric breakdown may occur in the dielectric layer between the leads.
An idea is disclosed in Japanese Patent Laid-Open No. 3-16250 to allow a large number of outer leads required to be used as described above. In this publication, two lead frames are used, with an outer lead of a second lead frame placed between the outer leads of a first lead frame. In this example, as illustrated in FIGS. 27 and 28, a smaller distance between the outer leads results in a smaller width of outer leads 11 (or 10) of the second (or first) lead frame, which are disposed between outer leads 10 (or 11) of the first (or second) lead frame, so that in some cases sufficient lead strength cannot be retained. On the other hand, when outer leads 10 and 11 are made thicker in width to obtain the necessary lead strength, the distance between the leads becomes larger, which results in a larger package size.
FIG. 29 illustrates a conventional package size. The figure shows a plan view of lead frame 26 after chip 4 has been bonded onto die pad 6 for the purpose of showing that the outer leads of the package which extend out are larger than the chip in size.
Such semiconductor devices described above, which have a vertical-type structure, have the problem that effective use cannot be made of the part of the die pad 6, to which the chip is bonded, which is disposed with respect to the suspension lead and adjacent to the D portion (in FIG. 29), the D portion being disposed adjacent to the chip and opposite to the outer leads 24. In particular, as illustrated in FIG. 30, when the chip occupies a larger area with respect to the package and the mounting density is high, there is the problem that the electrodes (bonding pads) on the chip, which is connected with the outer leads, are disposed on only one side of the chip.